In the field of integrated circuits, memory configurations may vary across a product family. For example, in an automotive instrument cluster family of products, high-end applications may require, for example, 8 MB of RAM (random access memory), while lower-end applications may require, for example, 1 MB of RAM. Conventionally, two approaches to providing different memory configurations across a product range have been used.
A first conventional approach involves ‘phantoming’ down the memory configuration from the high-end application to the lower-end applications, whereby unrequired memory is disabled for the lower-end applications. In this manner, only a single silicon mask set is created, but a lower gross margin is achievable for the lower-end products.
A second conventional approach is to create separate silicon mask sets for each required memory configuration. In this manner, an optimal, cost efficient memory configuration is achieved for the lower-end products. However, as the cost of new silicon mask sets is becoming an increasingly higher part of the overall product cost, the need to create new silicon mask sets for each individual product within a product range is becoming increasingly less desirable.
One example of addressing such a problem is to provide a semiconductor wafer consisting of a plurality of replicated integrated circuit (IC) modules having inter-module cross-wafer electrical connections, with the replicated IC modules being capable of being cut into IC dies consisting of multiple replicated IC modules. In this manner, IC dies consisting of different configurations of the replicated IC modules may be created from the semiconductor wafer based on where the semiconductor wafer is cut (sawn). Advantageously, such a semiconductor wafer is capable of providing IC dies for both high-end applications requiring functionality from multiple replicated IC modules, as well as for low-end applications requiring functionality from fewer (e.g. just one) replicated IC modules without having to resort to ‘phantoming’ the high-end application IC die configurations, and without having to create separate silicon mask sets for the differing application requirements.
In order to enable an external device to access the resources within such variably configurable replicated IC modules, one can use an adaptive means of addressing the individual replicated IC modules. However, standard addressing schemes require individual select lines to be routed to each mapped resource, adding significant cost and complexity to the inter-module cross-wafer electrical connections, or for each resource to be customised to respond to a unique address range, for example custom addresses being assigned using custom metal layers, fuses, non-volatile memory or other mechanisms that add cost and complexity to the replicated IC modules, or by way of custom addresses being allocated on system start-up that would add significant delay to the system start-up procedure.